Generally, reading and writing data to locations in physical memory devices include translation of a corresponding address into row and column coordinates within the memory devices. The transistors of the wordline decoding circuitry operate to decode address signals to the memory and assert the respective wordlines. Wordline decoding circuitry includes a wordline decoder output driver, which typically includes three or more transistors that perform the function of a logical AND. In a typical arrangement, the wordline decoder output driver is replicated for each wordline. For example, in a block of memory having 16 wordlines, four-transistor wordline decoder output drivers would include 64 transistors (32 p-type and 32 n-type) in addition to any supporting circuitry.
It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.